Our client is a fast-growing deep-tech company building a next-generation AI compute SoC, combining high-performance AI processing with advanced networking capabilities. They have 70+ engineers across Israel, Europe, and the US, and with their first silicon already taped out and functioning they are now expanding their VLSI team in Poland.

They are looking for a highly independent Senior VLSI Verification Engineer who can own a verification domain end-to-end and operate as an extension of the Israeli VLSI team. This is a senior, impact-heavy role requiring strong technical leadership, autonomy, and experience with complex SoCs.

What You Will Do

• Take full ownership of block/cluster verification from specification to sign-off.

• Build and evolve SystemVerilog UVM verification environments.

• Drive unit-level, subsystem, and full-chip verification flows.

• Define verification strategy and methodology for your domain.

• Collaborate closely with architecture, RTL, and AI compute teams (mostly IL-based).

• Work on a state-of-the-art SoC that includes NoC, CPU subsystems, PCIe, DMA, memory hierarchies, and AI accelerators.
  

What We’re Looking For

• 7+ years of ASIC/SoC pre-silicon verification (senior-level autonomy is essential).

• Deep knowledge of SystemVerilog and UVM.

• Experience building verification from scratch and owning a block/cluster.

• Hands-on experience across unit, subsystem, and full-chip verification.

• Solid understanding of SoC architecture.

• B.Sc./M.Sc. in Electrical or Computer Engineering.
  

Nice to Have

• AMBA/AXI, NoC, CPU subsystems, PCIe, DMA, networking hardware.

• Experience with AI/ML accelerators or high-throughput pipelines.

• Prior tape-out experience.
  

Why This Role Is Unique

• Work on a real AI compute SoC with a successfully taped-out first generation.

• High autonomy: you will operate as a senior extension of the IL VLSI team.

• Low bureaucracy, fast decision-making, strong engineering culture.

• Chance to influence architecture, methodology, and silicon quality.

• Direct access to the VP of VLSI and CEO—rare for a hardware role.

• Hybrid office in Kraków: typically 2 days/week on-site, flexible for non-local candidates.

• EU remote possible with occasional office visits.
  

Location

• Preferred: Kraków (hybrid).

• Possible: Anywhere in EU time zones with periodic travel to Kraków.
  

Hiring Process:

1. 30-minute prescreen call with an external recruiter – initial experience check and role alignment.

2. Initial phone interview (15–30 minutes) with the Site Manager in Poland.

3. 2–3 technical interviews with the VLSI team 

4. HR interview with the company’s HR representative.

5. Final decision & offer.
   

If you’re looking for depth, ownership, and the chance to build verification for cutting-edge AI silicon — we’d love to hear from you.